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data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator with fanout buffer 8T49N012 8T49N012 revision 1 08/21/14 1 ?2014 integrated device technology, inc. general description the 8T49N012 is a high performance clock generator with selectable lvpecl or single-ended outputs. the 8T49N012 can generate selectable frequencies from a crystal or a single-ended reference clock. the frequency is selected from the frequency selection table. excellent phase noise performance is maintained with idt?s fourth generation femtoclock ? ng pll technology. pin assignment 56-lead vfqfn, 8.0mm x 8.0mm x 0.9mm features ? fourth generation femtoclock ng pll technology ? three differential output banks: bank a: selectable between four pairs of lvpecl or four pairs of complementary lvcmos/lvttl outputs bank b: two pairs of lvpecl outputs bank c: six pairs of lvpecl outputs ? selectable clock input or crystal input. ? supports 25mhz fundamental crystal or 25mhz, 50mhz, 66.67mhz clock input ? selectable 156.25mhz, 125mhz, 100mhz clock for bank b and bank c outputs ? selectable 156.25mhz, 125mhz, 100mhz, 250mhz, 312.5mhz, 50mhz, 25mhz, 62.5mhz or 78.125mhz for bank a outputs ? pll lock indication (lvcmos output) ? rms phase jitter at 156.25mhz (12khz - 20mhz): 0.199ps (typical) ? power supply modes: core / output 3.3v / 3.3v 3.3v / 2.5v 2.5v / 2.5v ? -40c to 85c ambient operating temperature ? 56-lead vfqfn ? lead-free (rohs 6) packaging 8T49N012 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc lock fb_div reserved v cc nb_div v ee nqb1 qb1 nqb0 qb0 v cco_b nc_div v cco_c 42 41 40 39 38 37 36 35 34 33 32 31 30 29 qc0 nqc0 qc1 nqc1 v cco_c qc2 nqc2 v ee qc3 nqc3 qc4 nqc4 qc5 nqc5 15 16 17 18 19 20 21 22 23 24 25 26 27 28 se v cc xtal_sel ps_sel v cca v ee na_div1 na_div0 v cc_x xtal_out xtal_in v ee clk_in noe_b v ee qa0_cmos nqa0_cmos v cco_a qa1_cmos nqa1_cmos v ee qa2_cmos nqa2_cmos v cco_a qa3_cmos nqa3_cmos v ee noe_c 56 55 54 53 52 51 50 49 48 47 46 45 44 43
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 2 revision 1 08/21/14 block diagram na_div[1,0] nb_div lock qa0_cmos nqa0_cmos qa1_cmos nqa1_cmos qa2_cmos nqa2_cmos qa3_cmos nqa3_cmos qc0 nqc0 qc1 nqc1 qc2 nqc2 qc3 nqc3 nc_div se noe_b noe_c pulldown pulldown pulldown pulldown pulldown pulldown pulldown fb_div xtal_sel pulldown xtal_in xtal_out qc4 nqc4 qc5 nqc5 ps_sel pulldown clk_in 1/na pd + cp vco 1/m 1/nb 1/nc qb0 nqb0 qb1 nqb1 ps 0 1 xtal osc pulldown
revision 1 08/21/14 3 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet pin description and pin characteristic tables table 1. pin descriptions 1 number name type description 1 se input pulldown select pin for bank a outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 2v cc power core power supply pins. 3 xtal_sel input pulldown select reference source between the crystal or input clock. lvcmos/ lvttl interface levels. see the function configuration tables section. 4 ps_sel input pulldown pre scale divider selection. lvcmos/lvttl interface levels. see the function configuration tables section. 5v cca power analog supply for vco. 6v ee power negative power supply pin. 7 na_div1 input pulldown select output frequency for bank a outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 8 na_div0 input pulldown select output frequency for bank a outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 9v cc_x power crystal oscillator power supply pin. 10 xtal_out o/i crystal oscillator interface output. 11 xtal_in o/i crystal oscillator interface input. 12 v ee power negative power supply pin. 13 clk_in input pulldown single-ended input clock. lvcmos/lvttl interface levels. 14 noe_b input pulldown output enable for bank b outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 15 nc unused no connect pin. 16 lock output pll lock indicator. logic high indicates pll is locked. lvcmos/lvttl interface levels. see the function configuration tables section. 17 fb_div input pulldown feedback divider selection. lvcmos/lvttl interface levels. see the function configuration tables section. 18 reserved reserve reserve pin. do not connect. 19 v cc power core power supply pin. 20 nb_div input pulldown select output frequency for bank b outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 21 v ee power negative power supply pin. 22 nqb1 output differential bank b outputs. lvpecl interface levels. 23 qb1 output 24 nqb0 output differential bank b outputs. lvpecl interface levels. 25 qb0 output 26 v cco_b power bank b output power supply pin. 27 nc_div input pulldown select output frequency for bank c outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 28 v cco_c power bank c output power supply pin. 29 nqc5 output differential bank c outputs. lvpecl interface levels. 30 qc5 output
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 4 revision 1 08/21/14 31 nqc4 output differential bank c outputs. lvpecl interface levels. 32 qc4 output 33 nqc3 output differential bank c outputs. lvpecl interface levels. 34 qc3 output 35 v ee power negative power supply pin. 36 nqc2 output differential bank c outputs. lvpecl interface levels. 37 qc2 output 38 v cco_c power bank c output power supply pin. 39 nqc1 output differential bank c outputs. lvpecl interface levels. 40 qc1 output 41 nqc0 output differential bank c outputs. lvpecl interface levels. 42 qc0 output 43 noe_c input pulldown output enable for bank c outputs. lvcmos/lvttl interface levels. see the function configuration tables section. 44 v ee power negative power supply pin. 45 nqa3_cmos output selectable lvpecl differential or complementary lvcmos/lvttl bank a outputs. 46 qa3_cmos output 47 v cco_a power bank a output power supply pin. 48 nqa2_cmos output selectable lvpecl differential or complementary lvcmos/lvttl bank a outputs. 49 qa2_cmos output 50 v ee power negative power supply pin. 51 nqa1_cmos output selectable lvpecl differential or complementary lvcmos/lvttl bank a outputs. 52 qa1_cmos output 53 v cco_a power bank a output power supply pin. 54 nqa0_cmos output selectable lvpecl differential or complementary lvcmos/lvttl bank a outputs. 55 qa0_cmos output 56 v ee power negative power supply pin. e-pad v ee power negative power supply pin. note 1: pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 1. pin descriptions 1 (continued) number name type description table 2. pin characteristics symbol parameter test conditions minimum typical maximum units c in input capacitance input control pins 3.5 pf r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance (per output) v cc, v cc_x, v cco_a = 3.465v 6.5 pf v cc, v cc_x = 3.465v, v cco_a = 2.625v 6.5 pf rout lvcmos output impedance qa[0:3]_cmos, nqa[0:3]_cmos v cco_a =3.3v5% 26 ? v cco_a =2.5v5% 30 ?
revision 1 08/21/14 5 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet function configuration tables table 3a. fb_div function table fb_div feedback divider low (default) 50 mid 75 high 100 table 3b. se function table se bank a output low (default) differential output mid high impedance high lvcmos output table 3c. xtal_sel function table xtal_sel bank a output low (default) clk_in high xtal table 3d. lock indicaiotn table lock pll status low pll is out of lock high pll is locked table 3e. nqe_b function table noe_b bank b output low (default) lvpecl mid (reserved) reserved high high impedance table 3f. noe_c function table noe_c bank c output low (default) lvpecl mid (reserved) reserved high high impedance table 3g. bank b and c output divider table input frequency (mhz) ps_sel fb_div nb_div bank b frequency (mhz) nc_div bank c frequency (mhz) 25 low (default) low (default) low (default) 125 low (default) 125 mid 100 mid 100 high 156.25 high 156.25 66.66667 mid mid low (default) 125 low (default) 125 mid 100 mid 100 high 156.25 high 156.25 50 high low low (default) 125 low (default) 125 mid 100 mid 100 high 156.25 high 156.25
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 6 revision 1 08/21/14 table 3h. bank a output divider table input frequency (mhz) ps_sel fb_div na_div [1:0] bank a frequency (mhz) 25 low (default) low (default) low, low (default) 125 low, high 156.25 high, low 312.5 high, high 100 low, mid 25 high, mid 50 mid, low 250 mid, high 62.5 mid, mid 78.125 66.66667 mid mid low, low (default) 125 low, high 156.25 high, low 312.5 high, high 100 low, mid 25 high, mid 50 mid, low 250 mid, high 62.5 mid, mid 78.125 50 high low low, low (default) 125 low, high 156.25 high, low 312.5 high, high 100 low, mid 25 high, mid 50 mid, low 250 mid, high 62.5 mid, mid 78.125
revision 1 08/21/14 7 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc electrical characteristics or ac electrical characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 3.6v inputs, v i xtal_in other input 0v to 2v -0.5v to v cc + 0.5v outputs, v o (lvcmos) -0.5v to v cco_a + 0.5v outputs, i o (lvpecl) continuous current surge current 50ma 100ma thermal junction temperature, t j 125 qc storage temperature, t stg -65 q cto150 qc dc electrical characteristics item rating table 4a. power supply dc characteristics, v cc =v cc_x =v cco_x 1 = 3.3v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cc_x xtal supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v v cco_x output supply voltage 3.135 3.3 3.465 v i cca analog supply current 42 50 ma i ee power supply current unterminated outputs 332 381 ma note 1: v cco_x denotes v cco_a, v cco_b and v cco_c, table 4b. power supply dc characteristics, v cc =v cc_x =v cco_x 1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: v cco_x denotes v cco_a, v cco_b and v cco_c, symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cc_x xtal supply voltage 2.375 2.5 2.625 v v cca analog supply voltage 2.375 2.5 2.625 v v cco_x output supply voltage 2.375 2.5 2.625 v i cca analog supply current 32 41 ma i ee power supply current unterminated outputs 306 354 ma
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8 revision 1 08/21/14 table 4c. power supply dc characteristics, v cc =v cc_x = 3.3v 5%, v cco_x 1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: v cco_x denotes v cco_a, v cco_b and v cco_c, symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cc_x xtal supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v v cco_x output supply voltage 2.375 2.5 2.625 v i cca analog supply current 42 50 ma i ee power supply current unterminated outputs 323 373 ma table 4d. 2-level lvcmos/lvttl dc characteristics, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current clk_in, xtal_sel v cc =v in = 3.465v or 2.625v 150 a i il input low current clk_in, xtal_sel v cc = 3.465v or 2.625v, v in =0v -5 a v oh output high voltage qa[0:3]_cmos, nqa[0:3]_cmos, lock v cco_a = 3.465v; i oh = -8ma 2.6 v v ol output low voltage qa[0:3]_cmos, nqa[0:3]_cmos, lock v cco_a = 3.465v; i ol = 8ma 0.6 v table 4e. 3-level lvcmos/lvttl dc characteristics, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage 0.85 * v cc v v il input low voltage 0.15 * v cc v v im input middle voltage 0.45 * v cc 0.55 * v cc v i ih input high current noe_b, noe_c, na_divx, nb_div, nc_div, ps_sel, se v cc =v in = 3.465v or 2.625v 150 a i il input low current noe_b, noe_c, na_divx, nb_div, nc_div, ps_sel, se v cc = 3.465v or 2.625v, v in =0v -5 a i im input middle current noe_b, noe_c, na_divx, nb_div, nc_div, ps_sel, se v cc = 3.465v or 2.625v, v in = 0.5*v cc 150 a
revision 1 08/21/14 9 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet . table 4f. lvpecl dc characteristics, v cco_x 1 = 3.3v5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v oh output high voltage 2 v cco_x ? 1.1 v cco_x ? 0.7 v v ol output low voltage 2 v cco_x ? 2.0 v cco_x ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: v cco_x denotes v cco_a, v cco_b and v cco_c, note 2: outputs termination with 50 ? to v cco_x ?2v. table 4g. lvpecl dc characteristics, v cco_x 1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v oh output high voltage 2 v cco_x ? 1.1 v cco _x ? 0.7 v v ol output low voltage 2 v cco_x ? 2.0 v cco_x ? 1.5 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: v cco_x denotes v cco_a, v cco_b and v cco_c, note 2: outputs termination with 50 ? to v cco_x ?2v. table 5. crystal characteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf load capacitance (c l ) 12 18 pf
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 10 revision 1 08/21/14 ac electrical characteristics table 6. ac characteristics, v cc =v cc_x =v cco_x 1 = 3.3v 5% or 2.5v 5%, or v cc =v cc_x = 3.3v 5%, v cco_x 1 = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after thermal equilibrium has been reached under these conditions. symbol parameter test conditions minimum typical maximum units f in input frequency clk_in or xtal 25 mhz clk_in 50 mhz clk_in 66.67 mhz f vco vco frequency 2500 mhz t jit(?) lvpecl rms phase jitter, random 2 note 2: characterized using xtal input. 100mhz, integration range: 12khz ? 20mhz 320 415 fs 125mhz, integration range: 12khz ? 20mhz 210 270 fs 125mhz, integration range: 10khz ? 1mhz 163 220 fs 156.25mhz, integration range: 12khz ? 20mhz 199 260 fs 156.25mhz, integration range: 10khz ? 1mhz 165 225 fs 25mhz, integration range: 12khz ? 5mhz 245 415 fs t jit(?) lvcmos rms phase jitter, random 2 125mhz, integration range: 12khz ? 20mhz 210 280 fs 156.25mhz, integration range: 12khz ? 20mhz 204 265 fs 100mhz, integration range: 12khz ? 20mhz 312 385 fs tsk(o) output skew; note 3, 4 note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crosspoints. note 4: these parameters are guaranteed by characterization. lvpecl outputs same bank outputs 51 ps t r /t f output rise/fall time lvpecl outputs 20% - 80% 500 ps lvcmos outputs 20% - 80% 700 ps odc output duty cycle lvpecl outputs 45 50 55 % lvcmos outputs 45 50 55 %
revision 1 08/21/14 11 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet typical phase noise at 156.25mhz noise power (dbc / hz) offset frequency (hz) 156.25mhz rms phase jitter (random) 12khz to 20mhz = 0.199ps (typical)
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 12 revision 1 08/21/14 parameter measurement information 3.3v core/3.3v qax_cmos lvpecl output load test circuit 3.3v core/2.5v qax_cmos lvpecl output load test circuit lvcmos output duty cycle/pulse width/period 2.5v core/2.5v qax_cmos lvpecl output load test circuit 2.5v/2.5v qax_cmos output load test circuit output rise/fall time ferrite bead 2v -1.3v +0.165v v cca 2v v cc, v cco_x scope qx nqx v ee ferrite bead v cc 2.8v0.04v -0.5v0.125v v cca 2v 2.8v0.04v v cco_x nqax_cmos qax_cmos ferrite bead v cc 2v -0.5v0.125v v cca 2v v cco_x scope q0 ferrite bead -0.5v0.125% 2v v cc v cco_x 2v v cca v ee 20% 80% 80% 20% t r t f qax_cmos nqax_cmos
revision 1 08/21/14 13 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet parameter measurement information, continued rms phase jitter differential output duty cycle output skew lvpecl output rise/fall time nqx qx qx qy nqx nqy nqx qx
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 14 revision 1 08/21/14 applications information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clk input for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. a1k ? resistor can be used. outputs: lvpecl outputs all unused lvpecl output pairs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvcmos outputs all unused lvcmos outputs can be left floating. there should be no trace attached.
revision 1 08/21/14 15 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 1 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 1. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 16 revision 1 08/21/14 overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpecl driver to xtal input interface
revision 1 08/21/14 17 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figure 3a shows a layout that is recommended only as a guideline. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 3a. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? o =50 ? o =50 ? lvpecl input 3.3v 3.3v + _
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 18 revision 1 08/21/14 termination for 2.5v lvpecl outputs figure 4a and figure 4b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ?2v.forv cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 4b can be eliminated and the termination is shown in figure 4c . figure 4a. 2.5v lvpecl driver termination example figure 4b. 2.5v lvpecl driver termination example figure 4c. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ?
revision 1 08/21/14 19 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet schematic example figure 5 (next page) is an 8T49N012 application example schematic. the schematic focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure that the logic control inputs are properly set. in this example the device is operated at all v cc power pins = 3.3v. the bank a outputs are configured for lvcmos by pulling se high. three different examples of lvpecl terminations are shown for the outputs to demonstrate less common termination options. crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board. capacitive coupling to other conductors has two adverse effects. the first is that it reduces the oscillator frequency, leaving less tuning margin. second, noise on power planes and logic transitions on signal traces can pull the phase of voltages on the xtal_in and xtal_out pins of the oscillator. using a crystal on the top layer as an example, void all signal and power layers under the crystal, xtal_in, xtal_out and the input pins of the 8T49N012 between the top layer and the ground plane for the 8T49N012. if the ground plane for the 8T49N012 is the first layer under the crystal and the parasitic capacity of the traces and pads is excessive, then void enough power and signal planes to minimize the coupling capacity to the first ground plane. ensure that the ground under the crystal is the same ground as used for the tuning caps and the oscillator. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the 8T49N012 provides separate power supply pins to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the pcb as close to the power pins as possible. the 0.1f capacitors in each power pin filter must be placed on the device side. if space is limited, the other components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the v cc and v cco lc filters start to attenuate noise at approximately 10khz. if a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices.
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 20 revision 1 08/21/14 figure 5. 8T49N012 schematic example
revision 1 08/21/14 21 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet power considerations this section provides information on power dissipation and junction temperature for the 8T49N012i. equations and example calculations are also provided. 1. power dissipation the total power dissipation for the8T49N012 is the sum of the core power plus the output power dissipated due to the loading. the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. i ee = 344ma with qa bank in lvcmos mode is the worst case scenario. ? power (core) max =v cc_max *i ee = 3.465v * 0.345a = 1.195w ? power (lvpecl) max = 31mw per output ? total power (lvpecl) max =31mw*8= 0.248w lvcmos dynamic power dissipation ? dynamic power at 312.5mhz: p=c pd *freq*(v ddo ) 2 = 6.5pf * 312.5mhz * (3.465v) 2 p = 0.024w per output total power (cpd) = 0.024 w*8= 0.195w total power dissipation ? total powe r = power (core) + total power (lvpecl) + total power (cpd) = 1.195w + 0.248w+ 0.195w = 1.638w 2. junction temperature junction temperature, t j , is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, t j , to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: t j = ? ja * pd_total + t a t j = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 23.1 per ta b l e 7 below. c/w per table 6 below. therefore, t j for an ambient temperature of 85c with all outputs switching is: 85c + 1.638w * 23.1c/w = 122.8c. this is below the limit of 125c. this calculation is only an example. t j will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 56-lead vfqfn, forced convection ? ja vs. air flow meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 23.1c/w 20.2c/w 18.6c/w
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 22 revision 1 08/21/14 3. calculations and equations. the purpose of this section is to calculate the power dissipation for the lvpecl output pair. the lvpecl output driver circuit and termination are shown in figure 6 . v out v cco v cco -2v q1 rl 50
revision 1 08/21/14 23 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet reliability information transistor count the transistor count for 8T49N012 is 176,638 table 8. ? ja vs. air flow table for a 56-lead vfqfn ? ja vs. air flow meters per second 0 1 2.5 multi-layer pcb, jedec standard test boards 23.1c/w 20.2c/w 18.6c/w
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 24 revision 1 08/21/14 56-lead vfqfn package outline and package dimension
revision 1 08/21/14 25 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet 56-lead vfqfn package outline and package dimensions, continued
8T49N012 data sheet femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 26 revision 1 08/21/14 56-lead vfqfn package outline and package dimensions, continued
revision 1 08/21/14 27 femtoclock ? ng crystal-to-3.3v, 2.5v lvpecl/lvcmos clock generator 8T49N012 data sheet ordering information table 9. ordering information part/order number marking package shipping packaging temperature 8T49N012nlgi idt8T49N012nlgi ?lead-free? 56-lead vfqfn tray -40 ? cto85 ? c 8T49N012nlgi8 idt8T49N012nlgi ?lead-free? 56-lead vfqfn tape & reel -40 ? cto85 ? c
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